Real-time decoders are the classical bottleneck of fault-tolerant quantum computing. We are building an FPGA Relay belief-propagation decoder for bivariate-bicycle codes - the code family behind IBM's [[144,12,12]] "gross" code - using the same verified-generation flow as our classical LDPC products.
We publish progress the same way we publish products: measured, or labeled as a target.
| Milestone | Status |
|---|---|
| Floating-point golden model of Relay-BP (relay legs, ensemble, disordered memory strengths), exact against the published algorithm | DONE MEASURED |
| Convergence on circuit-level depolarizing noise, windowed decoding matrix (1008 checks × 8785 error mechanisms) | 100/100 trials MEASURED |
| Pipelined BP iteration on FPGA (2-cycle check/variable update) | 118 MHz MEASURED |
| Published FPGA reference implementation (for context) | 83 MHz |
| Mid-scale distance-5 decoder, fully parallel, synthesized | DONE MEASURED |
| Full gross-code real-time decoder, fixed-point, system integration | TARGET |
An honest negative result, because they matter: a fully parallel decoder at full gross-code scale does not fit synthesizable resource budgets - our folded dataflow reconstruction is bit-exact and is the path forward.
Quantum LDPC decoding is belief propagation on a quasi-cyclic code - exactly the structure our 5G NR and CCSDS generators already emit, verify, and timing-close. The quantum program reuses that proven machinery.
Decoder logical-error rates are statistical claims; they are only credible if the hardware is provably the same algorithm as the model that produced the curves. Our three-layer equivalence chain guarantees exactly that.
We are open to collaborations with quantum-hardware teams that need real-time decoding - co-development, evaluation on your syndrome streams, or a custom code family.
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